Improved Stability of 4H Sic-MOS Devices after Phosphorous Passivation with Etching Process

Y.K. Sharma; Yi Xu; M. R. Jennings; C Fisher; P. Mawby; L.C. Feldman; J.R. Williams

doi:10.14331/ijfps.2014.330064

Authors

Y.K. Sharma University of Warwick, Coventry, CV4 7AL UK Author
Yi Xu Department of Chemistry, Rutgers University, Piscataway, NJ 08854, USA Author
M. R. Jennings University of Warwick, Coventry, CV4 7AL UK Author
C Fisher University of Warwick, Coventry, CV4 7AL UK Author
P. Mawby University of Warwick, Coventry, CV4 7AL UK Author
L.C. Feldman Department of Chemistry, Rutgers University, Piscataway, NJ 08854, USA Author
J.R. Williams Physics Department, Auburn University, AL, 36849 USA Author

DOI:

https://doi.org/10.14331/ijfps.2014.330064

Keywords:

Silicon carbide, interface trap density, XPS, phosphosilicate glass

Abstract

Phosphorous passivation of the interface (4H-SiC/SiO₂) improves interface trap density (D_it) from 10¹³ eV^-1cm^-2 to 2×10¹²eV^-1cm^-2at 0.2eV below the conduction band edge of 4H-SiC. Due to the formation of phosphosilicate glass (PSG) layer during P passivation, metal-oxide-semiconductor capacitors (MOS-Cs) are highly unstable. Under bias-temperature stress (BTS) there is very large shift in the flatband voltage, V_FB, (independent of the bias polarity) of MOS-Cs. In this paper we proposed a new method to improve the stability of these devices. The PSG layer formed after passivation is etched-off in buffered oxide etch (BOE) and then capped with deposited oxide. Devices fabricated with this process showed D_it of 4x10¹²eV^-1cm^-2, and are stable after BTS test performed at 150^oC, +1.5MV/cm. This value of D_it is as good as the-state-of-the-art NO/N₂O passivated MOS-C. Also, XPS indicated the presence of P at the interface after etching which explains “NO/N₂O –like” D_it for etched PSG MOS-Cs.

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