Electrical Properties of the 3C-SiC/SiO2 Interface Grown With High Temperature Oxidation

Y.K. Sharma; F. Li, C.A. Fisher; M.R. Jennings; A. Perez-Tomas; S.M. Thomas; D. Hamilton; P.A. Mawby

doi:10.14331/ijfps.2014.330076

Authors

Y.K. Sharma School of Engineering, University of Warwick, Coventry, United Kingdom Author
F. Li, C.A. Fisher School of Engineering, University of Warwick, Coventry, United Kingdom Author
M.R. Jennings School of Engineering, University of Warwick, Coventry, United Kingdom Author
A. Perez-Tomas Institut Català de Nanociència i Nanotecnologia (ICN2), Campus de la UAB Author
S.M. Thomas School of Engineering, University of Warwick, Coventry, United Kingdom Author
D. Hamilton School of Engineering, University of Warwick, Coventry, United Kingdom Author
P.A. Mawby School of Engineering, University of Warwick, Coventry, CV4 7AL, UK Author

DOI:

https://doi.org/10.14331/ijfps.2014.330076

Keywords:

SiC, AFM, high temperature oxidation, interface trap density, C-V, G-V, bias-stress

Abstract

3C-Silicon carbide (SiC) metal-oxide-semiconductor (MOS) capacitors are fabricated to study the 3C-SiC/SiO₂ interface using standard hi-low capacitance-voltage (C-V) and conductance-voltage (G-V) methods. Devices are fabricated on an n-type 3C-SiC epilayer grown on a (100) oriented silicon (Si) substrate. Dry oxidation is done at different temperatures (1200^oC - 1400^oC) to grow the oxide layer. The 1300^oC as-oxidized device gives the lowest D_it of 5.8x10¹¹eV^-1cm^-2 at 0.25eV away from the conduction band (CB) edge. SIMS and AFM analyses of the devices have shown that there is no detrimental effect of high temperature oxidation on the oxide stoichiometry and surface roughness.

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