Authors: Y.K. Sharma, F. Li, C.A. Fisher, M.R. Jennings, A. Perez-Tomas, S.M. Thomas, D. Hamilton, P.A. Mawby
Affiliations: School of Engineering, University of Warwick, Coventry, United Kingdom, Institut Català de Nanociència i Nanotecnologia (ICN2), Campus de la UAB, Edifici ICN2 08193, Bellaterra (Barcelona), Catalonia, Spain
Emails: [email protected]
Journal: International Journal of Fundamental Physical Sciences (IJFPS)
Volume: 4, Issue: 4, Pages: 122-126, Date: December, 2014
ISSN: 2231-8186
DOI: https://doi.org/10.14331/ijfps.2014.330076
3C-Silicon carbide (SiC) metal-oxide-semiconductor (MOS) capacitors are fabricated to study the 3C-SiC/SiO2 interface using standard hi-low capacitance-voltage (C-V) and conductance-voltage (G-V) methods. Devices are fabricated on an n-type 3C-SiC epilayer grown on a (100) oriented silicon (Si) substrate. Dry oxidation is done at different temperatures (1200°C - 1400°C) to grow the oxide layer. The 1300°C as-oxidized device gives the lowest Dit of 5.8×10¹¹ eV⁻¹cm⁻² at 0.25 eV away from the conduction band edge. SIMS and AFM analyses of the devices show no detrimental effects of high temperature oxidation on oxide stoichiometry and surface roughness.
SiC, AFM, high temperature oxidation, interface trap density, C-V, G-V, bias-stress