Authors: Y.K. Sharma, Yi Xu, M. R. Jennings, C. Fisher, P. Mawby, L.C. Feldman, J.R. Williams
Affiliations: University of Warwick, Coventry, CV4 7AL UK, Department of Chemistry, Rutgers University, Piscataway, NJ 08854, USA, IAMDN, Rutgers University, Piscataway, NJ 08854, USA, Physics Department, Auburn University, AL, 36849 USA
Emails: [email protected]
Journal: International Journal of Fundamental Physical Sciences (IJFPS)
Volume: 4, Issue: 2, Pages: 37-42, Date: June, 2014
ISSN: 2231-8186
DOI: https://doi.org/10.14331/ijfps.2014.330064
Phosphorous passivation improves the interface trap density (Dit) at the 4H-SiC/SiO2 interface, but causes instability due to phosphosilicate glass (PSG) layer formation. This paper proposes etching off the PSG in buffered oxide etch (BOE) followed by capping with a deposited oxide to improve stability. The new method yields stable MOS-Cs with Dit of 4×10^12 eV^-1 cm^-2 and stable flatband voltage after bias-temperature stress (BTS). XPS shows P remains at the interface, accounting for NO/N2O-like Dit. The technique balances stability and passivation, offering improved fabrication of SiC MOS devices.
Silicon carbide, interface trap density, XPS, phosphosilicate glass